A fault tolerant NoC architecture with runtime adaptive double layer error control and crosstalk avoidance

@article{Vinodhini2015AFT,
  title={A fault tolerant NoC architecture with runtime adaptive double layer error control and crosstalk avoidance},
  author={M. Vinodhini and K. Lillygrace and N. S. Murty},
  journal={2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)},
  year={2015},
  pages={1-6}
}
This paper proposes fault tolerant Network on Chip (NoC) architecture which enables switching of error control coding scheme present in data link layer and network layer as needed, depending upon the rate of error at runtime. The proposed Joint Crosstalk Avoidance-Five Bit Error Correction-Six Bit Error Detection (JCA-FBEC-SBED) error control coding scheme is used in both the layers. This scheme provides crosstalk avoidance and also random and burst error correction up to 5 bits and detection… CONTINUE READING

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Key Quantitative Results

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