A faster approximation scheme for timing driven minimum cost layer assignment

@inproceedings{Hu2009AFA,
  title={A faster approximation scheme for timing driven minimum cost layer assignment},
  author={Shiyan Hu and Zhuo Li and Charles J. Alpert},
  booktitle={ISPD},
  year={2009}
}
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignment manifests enormous potential in drastically reducing wire delay. This is due the fact that wires on thick metals are much less resistive than those on thin metals. Nevertheless, it is not desired to assign all wires to thick metals and the right strategy is to only use minimal thick-metal routing resources for… CONTINUE READING

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