A fast routability-driven router for FPGAs

  title={A fast routability-driven router for FPGAs},
  author={Jordan S. Swartz and Vaughn Betz and Jonathan Rose},
  booktitle={FPGA '98},
Three factors are driving the demand for rapid FPGA compilation. First, as FPGAs have grown in logic capacity, the compile computation has grown more quickly than the compute power of the available computers. Second, there exists a subset of users who are willing to pay for very high speed compile with a decrease in quality of result, and accordingly being required to use a larger FPGA or use more real-estate on a given FPGA than is otherwise necessary. Third, very high speed compile has been a… 
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Automatic mapping tools for Triptych, an FPGA architecture with improved logic density and performance over commercial FPGAs, and extensions to these algorithms for mapping asynchronous circuits to Montage, the first FGPA architecture to completely support asynchronous and synchronous interface applications are described.
VPR: A new packing, placement and routing tool for FPGA research
In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which the authors can compare and presents placement and routing results on a new set of circuits more typical of today's industrial designs.
A detailed router for field-programmable gate arrays
The results show that C GE is able to route relatively large FPGAs in the absolute minimum number of tracks as determined by global routing, and that CGE has a linear run-time over circuit size.
Generation of synthetic sequential benchmark circuits
Comparing the post-lay out properties of the generated circuits with already existing circuits, it is demonstrated that the synthetic circuits are much more realistic than random graphs with the same number of nodes, edges and I/Os.
The RAW benchmark suite: computation structures for general purpose computing
  • J. BabbM. Frank A. Agarwal
  • Computer Science
    Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186)
  • 1997
The RAW benchmark suite consists of twelve programs designed to facilitate comparing, validating, and improving reconfigurable computing systems, and includes an architecture-independent compilation framework, Raw Computation Structures (RawCS), to express each algorithm's dependencies and to support automatic synthesis, partitioning, and mapping to a reconfigured computer.
Risa: Accurate And Efficient Placement Routability Modeling
An accurate and efficient placement routability modeling technique is proposed and incorporated into the prevailing simulated annealing approach based on the supply versus demand analysis of routing resource over an array of regions on a chip.
The Transmogrifier-2: a 1 million gate rapid prototyping system
The Transmogrifier-2 is a second generation multi-FPGA system that is modular and scalable, meaning that various sized systems can be constructed from the same board, while maintaining routability and the constant delay feature.
A Simple Yet Effective Technique for Global Wiring
  • R. Nair
  • Computer Science
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 1987
An implementation for global wiring of a structured custom chip design style is described along with results, and various parameters can be set to give preference to short routes or to reduce the time taken by the algorithm.
An Algorithm for Path Connections and Its Applications
  • C. Y. Lee
  • Computer Science, Mathematics
    IRE Trans. Electron. Comput.
  • 1961
The algorithm described in this paper is the outcome of an endeavor to answer the following question: Is it possible to find procedures which would enable a computer to solve efficiently
Plane parallel A* maze router and its application to FPGAs
  • M. Palczewski
  • Computer Science
    [1992] Proceedings 29th ACM/IEEE Design Automation Conference
  • 1992
A framework is established for unified code to support traditional wire routing, timing driven routing, and plane parallel and global routing for field programmable gate arrays.