A fast low-power modulo 2n+1 multiplier design

  title={A fast low-power modulo 2n+1 multiplier design},
  author={Rajashekhar Modugu and Minsu Choi and Nohpill Park},
  journal={2009 IEEE Instrumentation and Measurement Technology Conference},
Modulo 2n + 1 multipliers are the primitive computational logic components widely used in residue arithmetic, digital signal processing and cryptography. In this work, a fast low-power hardware implementation of modulo 2n + 1 multiplier is proposed and validated. The proposed hardware architecture is based on the efficient compressors and modulo carry look-ahead adders as the basic building blocks. The modulo carry lookahead adder uses the sparse-tree adder technique to achieve better speed… CONTINUE READING


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