A fast hardware/software co-verification method for systern-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication

@article{Nakamura2004AFH,
  title={A fast hardware/software co-verification method for systern-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication},
  author={Yuichi Nakamura and Kohei Hosokawa and Ichiro Kuroda and Ko Yoshikawa and Takeshi Yoshimura},
  journal={Proceedings. 41st Design Automation Conference, 2004.},
  year={2004},
  pages={299-304}
}
This paper describes a new hardware/software co-verification method for System-On-a-Chip, based on the integration of a C/C++ simulator and an inexpensive FPGA emulator. Communication between the simulator and emulator occurs via a flexible interface based on shared communication registers. This method enables easy debugging, rich portability, and high verification speed, at a low cost. We describe the application of this environment to the verification of three different complex commercial… CONTINUE READING
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