A fast digit-serial systolic multiplier for finite field GF(2m)

@inproceedings{Kim2005AFD,
  title={A fast digit-serial systolic multiplier for finite field GF(2m)},
  author={Chang Hoon Kim and Soonhak Kwon and Chun Pyo Hong},
  booktitle={ASP-DAC '05},
  year={2005}
}
This paper presents a new digit-serial systolic multiplier over GF(2m) for cryptographic applications. When input data come in continuously, the proposed array produces multiplication results at a rate of one every [m/D] + 2 clock cycles, where D is the selected digit size. Since the inner structure of the proposed array is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously… CONTINUE READING
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