A fast algorithm for power grid design


This paper presents an efficient heuristic algorithm to design a power distribution network of a chip by employing a successive partitioning and grid refinement scheme. In an iterative procedure, the chip area is recursively bipartitioned, and the wire pitches and the wire widths of the power grid in the partitions are repeatedly adjusted to meet the… (More)
DOI: 10.1145/1055137.1055153


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@inproceedings{Singh2005AFA, title={A fast algorithm for power grid design}, author={Jaskirat Singh and Sachin S. Sapatnekar}, booktitle={ISPD}, year={2005} }