A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture

@article{Fujii1999ADR,
  title={A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture},
  author={Takeo Fujii and K.-i. Furuta and Masato Motomura and Mitsuru Nomura and Makoto Mizuno and K.-i. Anjo and Kenichi Wakabayashi and Yuki Hirota and Y.-e. Nakazawa and Harunobu Ito and Masakazu Yamashina},
  journal={1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278)},
  year={1999},
  pages={364-365}
}
Reconfigurable logic LSIs, such as FPGAs, have been perceived as devices for prototyping and emulation. As the size and speed of FPGAs rapidly increase, however, they have begun to be used in /spl mu/P-based systems as reconfigurable accelerators. The idea is to achieve both hardware efficiency and software programmability by dynamically reconfiguring FPGAs. This idea, reconfigurable computing, provides an attractive solution especially for media/network-centric applications. Various types of… CONTINUE READING
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