Galois field arithmetic circuits find wide variety of application in cryptography. Thus they faces majority of the hardware based attacks for malicious gain. Though there are many approaches that have been proposed to mitigate such malicious attacks, most of them are inappropriate for practical applicability due to various design drawbacks. It is noted that Galois field multipliers are one among the many core arithmetic modules that are inevitable in the cryptography processors. Among them Montgomery multipliers are studied and implemented in applications like Elliptical Curve Cryptography arithmetic. However, a multiple bit error correctable Montgomery multiplier has not yet been implemented to this end. In this paper, we propose a novel multiple bit error correctable bit-parallel Montgomery multipliers with dynamic error detection and correction. First we present the BCH code based multiple bit error correctable Montgomery multiplier design architecture. Then we propose a novel scheme for reducing the recurrent delay when no transient malicious attack is present. In comparison with the existing multiple bit error correctable bit parallel multiplier structures, our novel technique significantly reduces the delay and improves the performance.