A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU

@inproceedings{Miura2001ADS,
  title={A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU},
  author={Seiji Miura and Kazushige Ayukawa and Takao Watanabe},
  booktitle={ISLPED},
  year={2001}
}
We have developed a dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. The scheme is based on two dynamic changes of SDRAM modes: from active standby to standby and from standby to active standby. It reduces both the operating current and the latency of an SDRAM. An analysis using benchmark programs shows that the developed scheme reduces the SDRAM operating current by 40% and latency by 38% compared to those of standby mode. An SDRAM controller was developed based… CONTINUE READING
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References

Publications referenced by this paper.

Sub-1-μA Dynamic Reference Voltage Generator for Battery-Operated DRAMs

  • H.Tanaka
  • 1993 Symposium on VLSI Circuits Digest of…
  • 1993
Highly Influential
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