A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop

@article{Cheng2004ADP,
  title={A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop},
  author={Kuo-Hsing Cheng and Wei-Bin Yang and Shu-Chang Kuo},
  journal={2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)},
  year={2004},
  volume={1},
  pages={I-777}
}
A dual-slope frequency detector and charge pump architecture to achieve fast locking of phased-locked loops is proposed and analyzed. The proposed topology is based on two tuning loops: a fine-tuning loop and a coarse-tuning loop. A course-tuning loop is used for fast convergence, and a fine-tuning loop is used to complete fine adjustments. The proposed PLL circuit is designed based on the TSMC 0.35 /spl mu/m 1P4M CMOS process with a 3.3V supply voltage. HSPICE simulation shows that the lock… CONTINUE READING
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