A dual precision IEEE floating-point multiplier

@article{Even2000ADP,
  title={A dual precision IEEE floating-point multiplier},
  author={Guy Even and Silvia M. M{\"u}ller and Peter-Michael Seidel},
  journal={Integration},
  year={2000},
  volume={29},
  pages={167-180}
}
We present a design of an IEEE oating-point multiplier capable of performing either a double-precision multiplication or a single-precision multiplication. In single-precision the la-tency is two clock cycles and in double-precision the latency is three clock cycles, where each pipeline stage contains roughly fteen logic levels. A single-precision multiplication can be followed immediately by another multiplication of either single or double-precision. A double-precision multiplication requires… CONTINUE READING
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