A dual execution pipelined floating-point CMOS processor

@article{Kowaleski1996ADE,
  title={A dual execution pipelined floating-point CMOS processor},
  author={J L Kowaleski and G. M. Wolrich and T. Fischer and R. Dupcak and P. L. Kroesen and Tung Pham and A I Olesin},
  journal={1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC},
  year={1996},
  pages={358-359}
}
A floating point unit initially implemented on a 300 MHz microprocessor in a 0.5 /spl mu/m/4-metal layer CMOS process and subsequently scaled for use in a 433 MHz version of the microprocessor in 0.35 /spl mu/m/4-metal layer CMOS process is described. This floating-point unit executes two floating-point instructions per cycle achieving 600 Mflops (peak) performance at 300 MHz and 366 Mflops (peak) at 433 MHz. It supports IEEE and VAX data types and rounding modes, including IEEE rounding to… CONTINUE READING
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