A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission

This paper presents the first CMOS dual bitrate chipset with equalization in transmitter and receiver as well as a clock to data skew adjustment. Both the transmitter and the receiver consume less power than those in previously published results in the works of Hosida et al. (2007).