A distributed interleaving scheme for efficient access to WideIO DRAM memory

@inproceedings{Seiculescu2012ADI,
  title={A distributed interleaving scheme for efficient access to WideIO DRAM memory},
  author={Ciprian Seiculescu and Luca Benini and Giovanni De Micheli},
  booktitle={CODES+ISSS},
  year={2012}
}
Achieving the main memory (DRAM) required bandwidth at acceptable power levels for current and future applications is a major challenge for System-on-Chip designers for mobile platforms. Three dimensional (3D) integration and 3D stacked DRAM memories promise to provide a significant boost in bandwidth at low power levels by exploiting multiple channels and wide data interfaces. In this paper, we address the problem of efficiently exploiting the multiple channels provided by standard (JEDEC's… CONTINUE READING

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