Modern telecommunication applications, such as the digital subscriber line (DSL) technologies require high-speed and high-resolution data converters. For the digital-to-analog converters (DACs) the requirements are around 12-14 bits of resolution and several MHz of signal bandwidth. The current-steering architecture is most often used, because it is suitable for high-speed operation. However, it usually suffers from linearity problems . We present the work on a so-called redundant differential current-steering architecture that allows the common-mode level of the signals to be varied. The current-steering DAC is described in Sec. 2. In Sec. 3 we present the proposed architecture, and simulations showing how the variable common-mode level can be utilized to reduce the impact of different nonlinearity sources are presented in Sec. 4. Finally, the paper is concluded in Sec. 5.