A differential DAC architecture with variable common-mode level


Modern telecommunication applications, such as the digital subscriber line (DSL) technologies require high-speed and high-resolution data converters. For the digital-to-analog converters (DACs) the requirements are around 12-14 bits of resolution and several MHz of signal bandwidth. The current-steering architecture is most often used, because it is suitable for high-speed operation. However, it usually suffers from linearity problems [1]. We present the work on a so-called redundant differential current-steering architecture that allows the common-mode level of the signals to be varied. The current-steering DAC is described in Sec. 2. In Sec. 3 we present the proposed architecture, and simulations showing how the variable common-mode level can be utilized to reduce the impact of different nonlinearity sources are presented in Sec. 4. Finally, the paper is concluded in Sec. 5.

DOI: 10.1109/ISCAS.2002.1009790

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@inproceedings{Andersson2002ADD, title={A differential DAC architecture with variable common-mode level}, author={K. Ola Andersson and Niklas U. Andersson and Mark Vesterbacka and J. Jacob Wikner}, booktitle={ISCAS}, year={2002} }