A design of high-performance pipelined architecture for H.264/AVC CAVLC decoder and low-power implementation

@article{Lee2010ADO,
  title={A design of high-performance pipelined architecture for H.264/AVC CAVLC decoder and low-power implementation},
  author={Byung-Yup Lee and Kwang-Ki Ryoo},
  journal={IEEE Transactions on Consumer Electronics},
  year={2010},
  volume={56}
}
In this paper, we propose a highly efficient VLSI architecture for context-based adaptive variable-length coding (CAVLC) decoder. In multimedia data processing systems, the real-time processing requirement is the most critical problem and the only requirement that must be satisfied. Thus, an architecture which has a short processing time though a high throughput, can meet the requirement at low operating frequencies. Consequently, the architecture can have an advantage of low power consumption… CONTINUE READING

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