A design methodology for the automatic sizing of standard-cell libraries

@inproceedings{Pilato2011ADM,
  title={A design methodology for the automatic sizing of standard-cell libraries},
  author={Christian Pilato and Fabrizio Ferrandi and Davide Pandini},
  booktitle={ACM Great Lakes Symposium on VLSI},
  year={2011}
}
Current EDA tools are often based on standard-cell libraries for the design of modern complex systems-on-chip. In general, there are opposite trends to compact and extend the standard cell libraries, and to move towards custom libraries, highly optimized for specific goals (e.g., area, timing or power consumption) or designs. We thus propose a design methodology for library sizing that combines decimation strategies and generation of cell variants. The proposed methodology is based on Simulated… CONTINUE READING

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Key Quantitative Results

  • This reduces the number of cells to be created by more the 90% in average and with a good improvement in the execution time, despite a minimal overhead in the quality of the results.

References

Publications referenced by this paper.
SHOWING 1-4 OF 4 REFERENCES

An evolutionary approach for standard-cell library reduction

  • ACM Great Lakes Symposium on VLSI
  • 2007
VIEW 8 EXCERPTS
HIGHLY INFLUENTIAL

FreePDK: An Open-Source Variation-Aware Design Kit

  • 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07)
  • 2007
VIEW 2 EXCERPTS
HIGHLY INFLUENTIAL

Improving cell libraries for synthesis

  • Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94
  • 1994
VIEW 3 EXCERPTS
HIGHLY INFLUENTIAL