A delay-encoding-logic array processor for dynamic programming matching

@article{Ogawa2004ADA,
  title={A delay-encoding-logic array processor for dynamic programming matching},
  author={Masashi Ogawa and Tadashi Shibata},
  journal={Proceedings of the 30th European Solid-State Circuits Conference},
  year={2004},
  pages={311-314}
}
Computationally very expensive, dynamic programming matching of data sequences has been directly implemented as a fully-parallel-architecture VLSI chip. The chip is organized as a 2D array of delay-encoding logic units, which works as an automatic best-match-sequence search network. The circuit operates as digital logic in the signal domain, while analog… CONTINUE READING