A configurable multiprocessor and dynamic load balancing for parallel LU factorization


Summary form only given. The exponentially increasing complexity of many scientific applications and the high cost of supercomputing force us to explore new, sustainable, and affordable high-performance computing platforms. Recent significant advances in FPGA technology and the inherent advantages of configurable logic have brought about new research efforts in the configurable computing field: parallel processing on configurable chips. We explore here parallel LU factorization of large sparse block-diagonal-bordered (BDB) matrices on a configurable multiprocessor that we have designed and implemented. A dynamic load balancing strategy is proposed and analyzed. Performance results for IEEE power test systems are provided. Our research provides evidence that configurable logic can be a viable alternative to high-performance scientific computing.

DOI: 10.1109/IPDPS.2004.1303282

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@article{Wang2004ACM, title={A configurable multiprocessor and dynamic load balancing for parallel LU factorization}, author={Xiaofang Wang and Sotirios G. Ziavras}, journal={18th International Parallel and Distributed Processing Symposium, 2004. Proceedings.}, year={2004}, pages={234-} }