A compiler framework for optimization of affine loop nests for gpgpus


GPUs are a class of specialized parallel architectures with tremendous computational power. The new Compute Unified Device Architecture (CUDA) programming model from NVIDIA facilitates programming of general purpose applications on their GPUs. However, manual development of high-performance parallel code for GPUs is still very challenging. In this paper, a number of issues are addressed towards the goal of developing a compiler framework for automatic parallelization and performance optimization of affine loop nests on GPGPUs: 1) approach to program transformation for efficient data access from GPU global memory, using a polyhedral compiler model of data dependence abstraction and program transformation; 2) determination of optimal padding factors for conflict-minimal data access from GPU shared memory; and 3) model-driven empirical search to determine optimal parameters for unrolling and tiling. Experimental results on a number of kernels demonstrate the effectiveness of the compiler optimization approaches developed.

DOI: 10.1145/1375527.1375562

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@inproceedings{Baskaran2008ACF, title={A compiler framework for optimization of affine loop nests for gpgpus}, author={Muthu Manikandan Baskaran and Uday Bondhugula and Sriram Krishnamoorthy and J. Ramanujam and Atanas Rountev and P. Sadayappan}, booktitle={ICS}, year={2008} }