A comparison of floating point and logarithmic number systems for FPGAs

@article{Haselman2005ACO,
  title={A comparison of floating point and logarithmic number systems for FPGAs},
  author={Michael Haselman and Michael J. Beauchamp and Aaron Wood and Scott Hauck and Keith D. Underwood and Karl S. Hemmert},
  journal={13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)},
  year={2005},
  pages={181-190}
}
There have been many papers proposing the use of logarithmic numbers (LNS) as an alternative to floating point because of simpler multiplication, division and exponentiation computations. However, this advantage comes at the cost of complicated, inexact addition and subtraction, as well as the need to convert between the formats. In this work, we created a parameterized LNS library of computational units and compared them to an existing floating point library. Specifically, we considered… 
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Different sizes of ROM are used for addition and subtraction and their performances are compared to the floating point.
ROM-less LNS
TLDR
Two algorithms are described, a new co-transformation procedure and an improvement to an existing interpolation method, that reduce these tables to an extent that allows their easy synthesis in logic.
LNS with Co-Transformation Competes with Floating-Point
TLDR
A new co-transformation procedure is described that eliminates much of the ROM space and allows the easy synthesis of the remainder in logic, and several interpolation methods that might benefit from it are evaluated.
A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic
TLDR
Two concurrent libraries of parameterized arithmetic operators, targeting recent field-programmable gate arrays, are presented, and are unbiased in the sense that they strive to reflect the state-of-the-art for both number systems.
Comparing floating-point and logarithmic number representations for reconfigurable acceleration
  • H. Fu, O. Mencer, W. Luk
  • Computer Science
    2006 IEEE International Conference on Field Programmable Technology
  • 2006
TLDR
A Stream Compiler, ASC as the hardware design and compilation tool, a convenient scheme to compare the designs of both floating-point and logarithmic numbers and select the solution with the best performance and accuracy, was developed.
Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis
TLDR
FPLibrary, a freely available, dual FP/LNS arithmetic operator library, is used in the prototype phase of an application to obtain accurate measures of performance, cost and accuracy of both LNS and FP approaches.
Design of a high precision logarithmic converter in a binary floating point divider
TLDR
The proposed piecewise interpolation method with differential coefficients for logarithmic conversion greatly reduces the error range and the throughput has been considerably improved with slightly increased gate counts, where the difference of the results is sufficiently tolerable for mobile 3D graphic applications.
A Novel Cotransformation for LNS Subtraction
TLDR
An overview of the family of LNS subtraction algorithms called “Cotransformations,” and a “Novel Cotransformation Combination” that offers improvements in terms of area and speed without sacrificing accuracy compared to previous methods is proposed.
DESIGN OF LOGARITHM BASED FLOATING POINT MULTIPLICATION AND DIVISION ON FPGA
TLDR
This work presents the design by using the same hardware for performing logarithmic operations, antilogarithm, rounding and exponential functions, which is found to be efficient in terms of area and speed compared to the design of conventional floating point arithmetic designs.
Arithmetic with the two-dimensional logarithmic number system (2dlns)
TLDR
2DLNS-based multiplication architectures with two different levels of recursion are presented, which are able to perform single and double precision multiplication, as well as fault tolerant and dual throughput single precision operations.
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