A comparison by simulation and by measurement of the substrate noise generated by CMOS, CSL, and CBL digital circuits

@article{Albuquerque2005ACB,
  title={A comparison by simulation and by measurement of the substrate noise generated by CMOS, CSL, and CBL digital circuits},
  author={Edgar F. M. Albuquerque and Manuel Medeiros Silva},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
  year={2005},
  volume={52},
  pages={734-741}
}
Current-steering logic (CSL) and current-balanced logic (CBL) are logic families that have been proposed with the objective of reducing the substrate noise in mixed-signal integrated circuits. These two families are compared here with conventional CMOS by simulation, using a substrate model extracted from the layouts, and also by measurements on a test chip. With small, low-power cells, noise reduction of CSL and CBL with respect to CMOS is only marginal; the same result is obtained with large… CONTINUE READING

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