A communication architecture for multiprocessor networks
@inproceedings{Bisiani1989ACA, title={A communication architecture for multiprocessor networks}, author={Roberto Bisiani and Andreas Nowatzyk}, year={1989} }
The system described in this thesis explores the territory between the two classical multiprocessor families: shared memory and message passing machines. Like shared memory systems, the proposed architecture presents the user a logically uniform address space shared by all processors. This programming model is supported directly by dedicated communication hardware that is translating memory references into messages that are exchanged over a network of point to point channels. The key parts ofâĤÂ
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12 Citations
Performance analysis of multiprocessor interconnection networks using a burst-traffic model
- Computer Science
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This thesis presents the development and use of a performance analysis methodology suitable for use in the evaluation of multiprocessor interconnection networks and shows that structure in oblivious routing is important, and several adaptive routing schemes perform equally well.
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- Computer ScienceProceedings 22nd Annual International Symposium on Computer Architecture
- 1995
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- Computer ScienceEuro-Par
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The design space for high performance cache coherency controllers is discussed and the architecture of the programmable protocol engines that were developed for the S3.mp shared memory multiprocessor is described.
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- Computer Science
- 1993
A simple and eecient scheme to model the performance of idealized adaptive routing, using an analytic queueing model which approximates its behavior and provides insight into the nature of message traac.
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- Computer ScienceProceedings of IEEE Scalable High Performance Computing Conference
- 1994
A general adaptive routing system for direct networks which can route the maximum number of messages out of a node at any time and is applied to the case of a two-dimensional k-ary n-cube, for which an approximate analytic queueing model is derived.
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This paper evaluates a basic, high-performance adaptive system using an analytic queueing model which approximates its behavior and provides insight into the nature of message delivery in a communication network.
Distributed synchronous clocking
- Computer ScienceProceedings Sixteenth Conference on Advanced Research in VLSI
- 1995
This paper presents an alternative approach to synchronous clocking that maintains the simplicity of synchronous operation without suffering the drawbacks of centralized clocking, and presents a simple method for eliminating mode-lock in k-ary Cartesian meshes.
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- Computer Science
- 1997
Simulation and analytic results are used to show that analysis based solely on average case times can be optimistic and lead to poor design decisions and self-timed meshes are asymptotically faster than synchronous ones.
Self-timed meshes are faster than synchronous
- Computer ScienceProceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems
- 1997
Self-timed meshes are asymptotically faster than synchronous ones and simulation and analytic results are used to show that analysis based solely on average case times can be optimistic and leads to poor design decisions.
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- Computer ScienceInternet Res.
- 1995
An integrated hardware and software system which uses Internet communications to enable remotely created bidders to participate in realâtime Dutch auctions and which meets the stringent requirement that synchrony be maintained among bidderâ terminals to ensure that each bidder has a fair chance to bid at the current offer price is described.
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