• Corpus ID: 26301397

A communication architecture for multiprocessor networks

@inproceedings{Bisiani1989ACA,
  title={A communication architecture for multiprocessor networks},
  author={Roberto Bisiani and Andreas Nowatzyk},
  year={1989}
}
The system described in this thesis explores the territory between the two classical multiprocessor families: shared memory and message passing machines. Like shared memory systems, the proposed architecture presents the user a logically uniform address space shared by all processors. This programming model is supported directly by dedicated communication hardware that is translating memory references into messages that are exchanged over a network of point to point channels. The key parts of… 

Performance analysis of multiprocessor interconnection networks using a burst-traffic model

This thesis presents the development and use of a performance analysis methodology suitable for use in the evaluation of multiprocessor interconnection networks and shows that structure in oblivious routing is important, and several adaptive routing schemes perform equally well.

S-Connect: from networks of workstations to supercomputer performance

The first version of the S-Connect switching element has been successfully, implemented in a commercial 0.65 /spl mu/m CMOS process.

Exploiting Parallelism in Cache Coherency Protocol Engines

The design space for high performance cache coherency controllers is discussed and the architecture of the programmable protocol engines that were developed for the S3.mp shared memory multiprocessor is described.

Analytical Models of Adaptive Routing

A simple and eecient scheme to model the performance of idealized adaptive routing, using an analytic queueing model which approximates its behavior and provides insight into the nature of message traac.

On the design of optimal adaptive routers for direct networks

  • A. LagmanW. Najjar
  • Computer Science
    Proceedings of IEEE Scalable High Performance Computing Conference
  • 1994
A general adaptive routing system for direct networks which can route the maximum number of messages out of a node at any time and is applied to the case of a two-dimensional k-ary n-cube, for which an approximate analytic queueing model is derived.

Analytical Models of Adaptive Routing Strategies Analytical Models of Adaptive Routing Strategies Modeling Adaptive Routing

This paper evaluates a basic, high-performance adaptive system using an analytic queueing model which approximates its behavior and provides insight into the nature of message delivery in a communication network.

Distributed synchronous clocking

  • G. PrattJohn Nguyen
  • Computer Science
    Proceedings Sixteenth Conference on Advanced Research in VLSI
  • 1995
This paper presents an alternative approach to synchronous clocking that maintains the simplicity of synchronous operation without suffering the drawbacks of centralized clocking, and presents a simple method for eliminating mode-lock in k-ary Cartesian meshes.

eshes Are Faster Than Synchronous

Simulation and analytic results are used to show that analysis based solely on average case times can be optimistic and lead to poor design decisions and self-timed meshes are asymptotically faster than synchronous ones.

Self-timed meshes are faster than synchronous

  • Peggy B. K. PangM. Greenstreet
  • Computer Science
    Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems
  • 1997
Self-timed meshes are asymptotically faster than synchronous ones and simulation and analytic results are used to show that analysis based solely on average case times can be optimistic and leads to poor design decisions.

Design of an Internet-based system for remote Dutch auctions

An integrated hardware and software system which uses Internet communications to enable remotely created bidders to participate in real‐time Dutch auctions and which meets the stringent requirement that synchrony be maintained among bidder’ terminals to ensure that each bidder has a fair chance to bid at the current offer price is described.

References

SHOWING 1-10 OF 114 REFERENCES

A cache coherence approach for large multiprocessor systems

A solution to the cache coherence problem specifically for shared bus multiprocessors that adapts dynamically to the reference pattern is presented and one of the first solutions of this kind is an extension of the adaptive shared bus approach described in this paper.

The shared memory hypercube

  • E. Brooks
  • Computer Science
    Parallel Comput.
  • 1988

Tradeoffs in Message Passing and Shared Memory Implementations of a Standard Cell Router

This paper considers two implementations of the LocusRoute standard cell routing program, one of which uses a message passing approach and the other uses a shared memory approach and relies on underlying coherence mechanisms, such as hardware cache coherence protocols, to keep the data consistent.

On Hot-Spot; Contention in Interconnection Networks

This paper describes an analytical model of hot-spot contention and quantifies its effect on the performance of a MIN with a circuit switching communication protocol, obtaining performance measures for a MIN in which partial paths are held during path building and one destination address is more frequently chosen by incoming traffic than other addresses.

VLSI Communication Components for Multicomputer Networks

Questions in the design of universal VLSI communication components to be used as the building blocks for constructing robust, high-bandwidth, point-to-point networks are discussed and mechanisms which efficiently transmit a single message to multiple destinations are seen to have a significant impact on performance in programs relying on global information.

A survey of commercial parallel processors

This paper compares eight commercial parallel processors along several dimensions from the standpoint of interconnection structures, memory configurations, and interprocessor communication.

Competitive management of distributed shared memory

  • David L. BlackAnoop GuptaW. Weber
  • Computer Science
    Digest of Papers. COMPCON Spring 89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage
  • 1989
The authors present and analyze algorithms for managing the distributed shared memory present in nonuniform-memory-access multiprocessors and related systems and sketch possible extensions to the algorithms to support additional hardware architectures and software programming models.

A framework for adaptive routing in multicomputer networks

This thesis examines the possibility of performing adaptive routing as an approach to further improving upon the performance and reliability of message-passing concurrent computers by exploiting the inherent path redundancy found in richly connected networks in order to perform fault-tolerant routing.

Comparing shared and distributed memory computers

“Hot spot” contention and combining in multistage interconnection networks

The technique of message combining was found to be an effective means of eliminating this problem if it arises due to lock or synchronization contention, severely degrading all memory access, not just access to shared lock locations, due to an effect the authors call tree saturation.
...