A combinational logic implementation of S-box of AES

@article{Shastry2011ACL,
  title={A combinational logic implementation of S-box of AES},
  author={P. V. Sriniwas Shastry and Anuja Agnihotri and Divya Kachhwaha and Jayasmita Singh and M. S. Sutaone},
  journal={2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)},
  year={2011},
  pages={1-4}
}
This paper presents a combinational logic based Rijndael S-box implementation for the SubByte transformation on ASIC. Combinational implementation of S-box results in low cost, small area occupancy and high throughput as compared to the typical ROM based lookup table implementation with fixed and unbreakable access time. S-box has been implemented using 0.18µm CMOS standard cell library at 1.62V and runs at clock frequency of 71.43MHz. We could achieve throughput of 571.5Mbps with core… CONTINUE READING

Citations

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