A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications

@article{Chen2006ACG,
  title={A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications},
  author={Pao-Lung Chen and Ching-Che Chung and Jyh-Neng Yang and Chen-Yi Lee},
  journal={IEEE Journal of Solid-State Circuits},
  year={2006},
  volume={41},
  pages={1275-1285}
}
This work presents a clock generator with cascaded dynamic frequency counting (DFC) loops for wide multiplication range applications. The DFC loop, which uses variable time period to estimate and tune the frequency of the digitally controlled oscillator (DCO), enhances the resolution of frequency detection. The conventional phase-frequency detector (PFD) and programmable divider are replaced with a digital arithmetic comparator and a DCO timing counter. The value in the DCO timing counter is… CONTINUE READING
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