A characterization tool for current degradation effects of abnormally structured MOS transistors


A new modeling methodology and an environment for abnormally structured MOS transistors we presented. This methodology uses a three-dimensional device simulator and a curve fitting method to characterize the current degradation effects by extracting the parasitic diffusion resistance from abnormal transistors. We have applied this methodology to 0.5 /spl mu/m process. Within 5% error, an overall I-V curve fit for various device shapes and bias conditions is achieved. This methodology improves the accuracy of circuit-level simulation.

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