A characterization tool for current degradation effects of abnormally structured MOS transistors

Abstract

A new modeling methodology and an environment for abnormally structured MOS transistors we presented. This methodology uses a three-dimensional device simulator and a curve fitting method to characterize the current degradation effects by extracting the parasitic diffusion resistance from abnormal transistors. We have applied this methodology to 0.5 /spl mu/m process. Within 5% error, an overall I-V curve fit for various device shapes and bias conditions is achieved. This methodology improves the accuracy of circuit-level simulation.

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Cite this paper

@article{Park1997ACT, title={A characterization tool for current degradation effects of abnormally structured MOS transistors}, author={Jin-Kyu Park and Chang-Hoon Choi and Young-Kwan Park and Chang-Sub Lee and Jeong-Taek Kong and Moon-Ho Kim and Kyung-Ho Kim and Taek-Soo Kim and Sang-Hoon Lee}, journal={SISPAD '97. 1997 International Conference on Simulation of Semiconductor Processes and Devices. Technical Digest}, year={1997}, pages={41-43} }