A characterization of ten rasterization techniques

@inproceedings{Gharachorloo1989ACO,
  title={A characterization of ten rasterization techniques},
  author={N. Gharachorloo and S. Gupta and R. Sproull and I. Sutherland},
  booktitle={SIGGRAPH '89},
  year={1989}
}
With widespread use of raster scan displays and the ever-increasing desire for faster interactivity, higher image complexity, and higher resolution in displayed images, several techniques have been proposed for rasterizing primitive graphical objects. This paper characterizes the performance of these techniques and shows how they evolve for more complex images on higher resolution displays. This characterization will not only show the strengths and deficiencies of existing rasterization… Expand
An Efficient Massively Parallel Rasterization Scheme For a High Performance Graphics System
TLDR
The IMOGENE II system, a massively parallel Multi-SIMD graphics system, uses a new rasterization scheme combining Object Parallelism and Parallel Virtual Buffers, which leads to a better efficiency than other massively parallel SIMD systems, and allows a cost-effective, powerful and easily expandable system to be designed. Expand
High-Speed Rendering using Scan-Line Image Composition
TLDR
The object of this proposed research is to demonstrate that scalability over a wide performance range, low latency, and flexibility for many alternative input streams, such as volume data, and transparent surfaces can be achieved in a realizable system. Expand
Polygon rendering for interactive visualization on multicomputers
TLDR
A new polygon rendering algorithm is designed that uses the frame-to-frame coherence of the screen image to evenly partition the rasterization at reasonable cost and improves the algorithm's performance on systems with more than 64 processors. Expand
Forward rasterization
TLDR
Two forward rasterization algorithms are presented, one that renders quadrilaterals and is suitable for scenes modeled with depth images like in image-based rendering by 3D warping, and one that rendering triangles and is suited for scenes modeling conventionally. Expand
A high-performance distributed graphics system
TLDR
This paper examines how high performance graphics can be provided economically by the combined use of carefully selected processing facilities and discusses the benefits for incremental image specification systems which could be gained from implementation on such a hardware platform. Expand
Harnessing Parallelism for High-Performance Interactive Computer Graphics
This paper provides a summary of the Pixel-Planes project from its inception in 1980 to the present (1996). The goals of the project have been to advance the state of the art in interactive computerExpand
A sorting classification of parallel rendering
TLDR
A classification scheme is described that is based on where the sort from object coordinates to screen coordinates occurs, which it is believed is fundamental whenever both geometry processing and rasterization are performed in parallel. Expand
Method of Tile Visualization Technology with Sorting of Scene Fragments
TLDR
The method of tile visualization implemented in modern GPUs are described and the main rasterization techniques, mosaic and non-mosaic edge cases of scenes, ways of parallelization of the computational process are considered. Expand
Selecting the Optimal Tile Size for Low-Power Tile-Based Rendering
TLDR
This paper analyzes rendering techniques suitable for low power devices, and one technique that looks promising is Tile Rendering, which decomposes a scene into tiles and renders each tile independently. Expand
Dynamic Load Balancing within a High Performance Graphics System
  • H. Selzer
  • Computer Science
  • Advances in Computer Graphics Hardware
  • 1991
TLDR
A graphics processor architecture with a high degree of parallelism connected to a distributed frame buffer that can be configured with an arbitrary number of identical, high level programmable processors operating in parallel is described. Expand
...
1
2
3
4
5
...

References

SHOWING 1-10 OF 48 REFERENCES
A cell organized raster display for line drawings
TLDR
A display is described which extends the capabilities of this organization to include general graphics, and the feasibility of such a display is shown by deriving the minimum number of patterns required in the read only memory of the character generator to synthesize an arbitrary line. Expand
A VLSI architecture for updating raster-scan displays
TLDR
This paper describes an on-going project at Carnegie-Mellon University in which a frame buffer raster-scan display system is designed which has the high performance typically required for interactive display applications. Expand
A real time visible surface algorithm
TLDR
The dissertation describes an algorithm designed for a hardware processor capable of displaying solid objects, and a FORTRAN 5 program for simulating the hardware processor. Expand
Subanosecond pixel rendering with million transistor chips
TLDR
The design of a VLSI chip and a graphics system that can sustain sub-nanosecond pixel rendering rates for three-dimensional polygons and can be used to render about a million Z-Buffered and Gourard shaded polygons per second is presented. Expand
3D Graphics for Consumer Applications: How Realistic Does it Have to Be?
  • P. Winser
  • Computer Science
  • Advances in Computer Graphics Hardware
  • 1987
TLDR
The likely requirements for a consumer aimed real time 3D graphics system are stated in terms of performance and rendering techniques, and a research prototype of a 3D display processor is presented. Expand
Architectures and algorithms for parallel updates of raster scan displays
TLDR
The symmetric square organization which allows the access of square regions of the display is advocated which is shown to be indeed better than the scan-line organization. Expand
A fast shaded-polygon renderer
TLDR
A one-chip VLSI implementation of a shaded-polygon renderer which provides an affordable solution to the bottleneck of image rendering and its derivation and implementation in a pipelined, polygon-rendering chip are described. Expand
Dynamic scan-converted images with a frame buffer display device
TLDR
A color interactive display system which produces images of three-dimensional polygons and labels on a frame buffer display device is being developed, and a rate of 3 frames per second has been found sufficient to provide feedback to continuous user input. Expand
Memory Design for Raster Graphics Displays
  • M. Whitton
  • Computer Science
  • IEEE Computer Graphics and Applications
  • 1984
This tutorial examines the origin and nature of the problem of contention for memory cycles¿a problem that impacts the image update performance of every raster graphics system.
All Points Addressable Raster Display Memory
TLDR
This paper presents features of a customized dynamic RAM chip which can readily provide the necessary bandwidth and thus greatly simplify the design of very high performance APA raster scan displays and describes the second port for the video refresh, which makes the primary port available for update almost continuously. Expand
...
1
2
3
4
5
...