Sharing the instruction cache among lean cores on an asymmetric CMP for HPC applications
- Ugljesa Milic, Alejandro Rico, Paul M. Carpenter, Alex Ramírez
- 2017 IEEE International Symposium on Performance…
- 2017
1 Excerpt
A case for shared instruction cache on chip multiprocessors running OLTP
- Published 2003 in SIGARCH Computer Architecture News
Abstract
Due to their large code footprint, OLTP workloads suffer from significant I-cache miss rates on contemporary microprocessors. This paper analyzes the I-stream behavior of an OLTP workload, called the Oracle Database Benchmark (ODB), on Chip-Multiprocessors (CMP). Our results show that, although, the overall code footprint of ODB is large, multiple ODB… (More)