A capacitorless twin-transistor random access memory (TTRAM) on SOI

  title={A capacitorless twin-transistor random access memory (TTRAM) on SOI},
  author={Fukashi Morishita and Hideyuki Noda and Takayuki Gyohten and Mako Okamoto and Takashi Ipposhi and Shigeto Maegawa and Katsumi Dosaka and Kazutami Arimoto},
  journal={Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.},
  • F. Morishita, H. Noda, +5 authors K. Arimoto
  • Published 18 September 2005
  • Computer Science
  • Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.
We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2Mb test device has been fabricated on 130nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100ms at 80/spl deg/C. TTRAM process is compatible with the conventional SOI-CMOS and never requires any additional processes. A 6.1ns row-access time is achieved and 250MHz operation can be realized by using 2bank 8b-burst mode. 
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    2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)
  • 2002
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Test chip photograph Table I. CHIP FEATURES NE 0$7
  • Fig