A bit-serial approximate min-sum LDPC decoder and FPGA implementation

@article{Darabiha2006ABA,
  title={A bit-serial approximate min-sum LDPC decoder and FPGA implementation},
  author={Ahmad Darabiha and Anthony Chan Carusone and Frank R. Kschischang},
  journal={2006 IEEE International Symposium on Circuits and Systems},
  year={2006},
  pages={4 pp.-}
}
We propose a bit-serial LDPC decoding scheme to reduce interconnect complexity in fully-parallel low-density parity-check decoders. Bit-serial decoding also facilitates efficient implementation of wordlength-programmable LDPC decoding which is essential for gear shift decoding. To simplify the implementation of bit-serial decoding we propose a new approximation to the check update function in the min-sum decoding algorithm. The new check update rule computes only the absolute minimum and… CONTINUE READING
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References

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Showing 1-10 of 16 references

Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity

IEEE Transactions on Circuits and Systems II: Express Briefs • 2008
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IEEE Transactions on Communications • 2006
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Block - Iterations per frame 15 interlaced fully - parallel LDPC decoders with reduced interconnect com - Wordlength ( bits ) 3 plexity

A. Chan Carusone, F. R. Kschischang
2005

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V. Gaudet, A. Rapley
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