A Wide-Range Burst Mode Clock and Data Recovery Circuit

@article{Chen2006AWB,
  title={A Wide-Range Burst Mode Clock and Data Recovery Circuit},
  author={Wei-Zen Chen and Chin-Yuan Wei and Jen-Wen Chen},
  journal={2006 IEEE Asian Solid-State Circuits Conference},
  year={2006},
  pages={403-406}
}
This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 mum CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier… CONTINUE READING