A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI

@article{Tierno2008AWP,
  title={A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI},
  author={J C Tierno and A. V. Rylyakov and D. J. Friedman},
  journal={IEEE Journal of Solid-State Circuits},
  year={2008},
  volume={43},
  pages={42-51}
}
An all static CMOS ADPLL fabricated in 65 nm digital CMOS SOI technology has a fully programmable proportional-integral-differential (PID) loop filter and features a third order delta sigma modulator. The DCO is a three stage, static inverter based ring oscillator programmable in 768 frequency steps. The ADPLL lock range is 500 MHz to 8 GHz at 1.3 V and 25degC, and 90 MHz to 1.2 GHz at 0.5 V and 100degC. The IC dissipates 8 mW/GHz at 1.2 V and 1.6 mW/GHz at 0.5 V. The synthesized 4 GHz clock… CONTINUE READING
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A 10 b 10 GHz digitally controlled LC oscillator in 65 nm CMOS

  • N. Da Dalt, C. Kropf, M. Burian, T. Hartig, H. Elu
  • IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 188…
  • 2006
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