A Wide-Band Digital Phase-Locked Looop

@article{Ambarish2006AWD,
  title={A Wide-Band Digital Phase-Locked Looop},
  author={Shilpa Ambarish and Mahmoud Fawzy Wagdy},
  journal={Third International Conference on Information Technology: New Generations (ITNG'06)},
  year={2006},
  pages={597-598}
}
A high speed digital phase-locked loop (DPLL) is designed using 0.18..m CMOS process, using a 3.3V power supply. It operates in the frequency range 55MHz — 1.43GHz. A (PFD) phase frequency detector has a zero dead-zone by including delay elements in the Reset path. The current source used in the charge pump makes it insensitive to supply variations and provides ripple-free control voltage for the VCO (voltage controlled oscillator), which provides low jitter and no overshoot in locking… CONTINUE READING