A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V$_{\min}$ Lowering Techniques and Deep Sleep Mode

@article{Kim2009AVS,
  title={A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V\$_\{\min\}\$ Lowering Techniques and Deep Sleep Mode},
  author={Tae-Hyoung Kim and Jian Liu and C. H. Kim},
  journal={IEEE Journal of Solid-State Circuits},
  year={2009},
  volume={44},
  pages={1785-1795}
}
A voltage scalable 0.26 V, 64 kb 8T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Utilization of the reverse short channel effect in a SRAM cell design improves cell write margin and read performance without the aid of peripheral circuits. A marginal bitline leakage compensation (MBLC) scheme compensates for the bitline leakage current which becomes comparable to a read current at subthreshold supply voltages. The MBLC allows us to lower Vmin to 0.26 V and also… CONTINUE READING
Highly Cited
This paper has 71 citations. REVIEW CITATIONS
53 Citations
17 References
Similar Papers

Citations

Publications citing this paper.
Showing 1-10 of 53 extracted citations

71 Citations

051015'11'13'15'17
Citations per Year
Semantic Scholar estimates that this publication has 71 citations based on the available data.

See our FAQ for additional information.

References

Publications referenced by this paper.
Showing 1-10 of 17 references

A 256 kb sub-threshold SRAM using 65 nm CMOS

  • B. H. Calhoun, A. Chandrakasan
  • IEEE Int. Solid-State Circuits Conf. Dig., Feb…
  • 2006
Highly Influential
5 Excerpts

A 1.1 GHz 12/Mb-leakage SRAM design in 65 nm ultra-low-power CMOS technology with integrated leakage reduction for mobile applications

  • Y. Wang
  • IEEE J. Solid-State Circuits, vol. 43, no. 1, pp…
  • 2008

A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65 nm CMOS

  • L. Chang
  • Symp. VLSI Circuits Dig., Jun. 2007, pp. 252–253.
  • 2007
2 Excerpts

Similar Papers

Loading similar papers…