A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V$_{\min}$ Lowering Techniques and Deep Sleep Mode

  title={A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V\$_\{\min\}\$ Lowering Techniques and Deep Sleep Mode},
  author={Tae-Hyoung Kim and Jian Liu and C. H. Kim},
  journal={IEEE Journal of Solid-State Circuits},
A voltage scalable 0.26 V, 64 kb 8T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Utilization of the reverse short channel effect in a SRAM cell design improves cell write margin and read performance without the aid of peripheral circuits. A marginal bitline leakage compensation (MBLC) scheme compensates for the bitline leakage current which becomes comparable to a read current at subthreshold supply voltages. The MBLC allows us to lower Vmin to 0.26 V and also… CONTINUE READING
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