A Variation-Tolerant Multi-Level Memory Architecture Encoded in Two-state Memristors

Abstract

Memristors are becoming a promising non-CMOS high-density memory solution as CMOS technology approaches atomic limits. However, high electrical variability of both memristors and the analog reading circuitries cause significant error rates and the use of transistors limits the density of memristor/transistor hybrid architectures. This work presents a multi-memristor cell design that is robust while retaining the simplicity of non-feedback memristor programming. The proposed architecture offers a high bit density compared to other memristor/transistor hybrid architectures by introducing multilevel outputs to store multiple bits per cell, and has competitive power and read speed to existing architectures.

Showing 1-10 of 14 references

Electrical performance and scalability of pt dispersed SiO 2 nanometallic resistance switch

  • B J Choi, A C Torrezan, K J Norris
  • 2013

Engineering nonlinearity into memristors for passive crossbar applications

  • J Yang, M.-X Zhang, M D Pickett
  • 2012

Proc. IEEE

  • M.-S Wong, H Lee, S Yu
  • 2012

10x10nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation

  • B Govoreanu, G S Kar, Y-Y Chen
  • 2011