A Variation-Tolerant Multi-Level Memory Architecture Encoded in Two-state Memristors

Abstract

Memristors are becoming a promising non-CMOS high-density memory solution as CMOS technology approaches atomic limits. However, high electrical variability of both memristors and the analog reading circuitries cause significant error rates and the use of transistors limits the density of memristor/transistor hybrid architectures. This work presents a multi-memristor cell design that is robust while retaining the simplicity of non-feedback memristor programming. The proposed architecture offers a high bit density compared to other memristor/transistor hybrid architectures by introducing multilevel outputs to store multiple bits per cell, and has competitive power and read speed to existing architectures.

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Cite this paper

@inproceedings{Wu2016AVM, title={A Variation-Tolerant Multi-Level Memory Architecture Encoded in Two-state Memristors}, author={Bin Wu and Matthew R. Guthaus}, year={2016} }