A VLSI architecture for advanced video coding motion estimation

@article{Yap2003AVA,
  title={A VLSI architecture for advanced video coding motion estimation},
  author={Swee Yeow Yap and John V. McCanny},
  journal={Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003},
  year={2003},
  pages={293-301}
}
  • S. Y. Yap, J. McCanny
  • Published 24 June 2003
  • Computer Science
  • Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003
With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding (AVC), particularly in area of variable block searching motion estimation (VBSME), are increasing. This has led to research into suitable flexible hardware architectures to perform the various types of VBSME. We propose a new 1-D VLSI architecture for full search variable block size motion estimation (FSVBSME). The variable block size, sum of absolute differences (SAD) computation is… 

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