A VLSI architecture for a high-speed computation of the 1D discrete wavelet transform

@article{Zhang2005AVA,
  title={A VLSI architecture for a high-speed computation of the 1D discrete wavelet transform},
  author={Chengjun Zhang and Chunyan Wang and M. Omair Ahmad},
  journal={2005 IEEE International Symposium on Circuits and Systems},
  year={2005},
  pages={1461-1464 Vol. 2}
}
An efficient VLSI architecture for the computation of the convolution-based discrete wavelet transform (DWT) is presented. The proposed architecture, employing two processing elements and a single buffer in a pipeline mode, enhances the processing time by appropriately decomposing the overall computations and distributing them equally between the two processing elements. The data flow, both within and between the processing elements, is streamlined, making use of the buffer and employing… CONTINUE READING

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