A VLSI analog computer/math co-processor for a digital computer

  title={A VLSI analog computer/math co-processor for a digital computer},
  author={G. Cowan and Robert C. Melville and Yannis P. Tsividis},
  journal={ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.},
  pages={82-586 Vol. 1}
  • G. Cowan, R. Melville, Y. Tsividis
  • Published 2005
  • Computer Science, Engineering
  • ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.
A single-chip VLSI analog computer having 80 integrators and 336 other programmable linear and nonlinear circuits is fabricated in a 0.25 /spl mu/m CMOS process. The chip can be used to accelerate a digital computer's numerical routines. The IC is 1 cm/sup 2/ and consumes 300 mW. 

A VLSI analog computer/digital computer accelerator

The design of a single-chip VLSI analog computer fabricated in a 0.25-/spl mu/m CMOS process is described, used to simulate ordinary differential equations (ODEs), partial differential equations, and stochastic differential equations with moderate accuracy, significantly faster than a modern workstation.

About using analog computers in today's largest computational challenges

Analog computers can be revived as a feasible technology platform for low precision, energy efficient and fast computing by measuring the performance of a modern analog computer and comparing it with that of traditional digital processors.

Continuous-time DSPs, analog/digital computers and other mixed-domain circuits

This paper reviews recent research, involving circuits and systems which mix domains traditionally kept separate, and it is argued that by mixing domains one can have advantages which would not otherwise be possible.

Solving systems of linear equations on analog computers

This article outlines a technique making it possible to employ analog computers to the solution of linear equations, and uses these as initial vectors for a classic iterative algorithm running on the digital computer to further enhance the precision of the solution obtained.

Analog Representations in Digital Arithmetic: A Review

  • B. Parhami
  • Computer Science
    2018 52nd Asilomar Conference on Signals, Systems, and Computers
  • 2018
This paper reviews number representation schemes that are based on the analog encoding of numeric values in an otherwise digital arithmetic system, showing them to be closer than ever to practical realizability.

Continuous-time hybrid computation with programmable nonlinearities

This work presents the first continuous-time hybrid computing unit in 65nm CMOS, capable of solving nonlinear differential equations up to 4th order, and scalable to higher orders, and uses it in a low-power cyber-physical systems application.

Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time

A unit that performs continuous-time hybrid approximate computation, in which both analog and digital signals are functions of continuous time, is presented, capable of solving nonlinear differential equations up to 4th order, and is scalable to higher orders.

A Radio Frequency Analog Computer for Computational Electromagnetics

Software-programmable analog computing is proposed for power- and area-efficient acceleration of computational electromagnetics. All-pass filters are employed to realize a continuous-time

Reconfigurable Digital/Analog Processor Array for the Simulation of Gene Regulatory Networks

A prototype of an efficient platform which combines a general FPGA architecture with fairly simple, specialized and configurable computational elements is presented and it is shown how the prototype can be configured to simulate two simple example networks.

Evaluation of an Analog Accelerator for Linear Algebra

A reconfigurable analog accelerator for solving systems of linear equations is presented and it is found that the analog accelerator approach may be an order of magnitude faster and provide one third energy savings, depending on the accelerator design.



A CMOS Field-programmable Analog Array

  • E.K.F. LeeP. Gulak
  • Engineering
    1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
  • 1991
The design details and test results of a field-programmable analog array (FPAA) prototype chip in 1.2- mu m CMOS are presented. The analog array is based on subthreshold circuit techniques and

Analog VLSI Implementation of Neural Systems

  • C. MeadM. Ismail
  • Computer Science
    The Kluwer International Series in Engineering and Computer Science
  • 1989
A Neural Processor for Maze Solving and Issues in Analog VLSI and MOS Techniques for Neural Computing are discussed.

A CMOS general-purpose sampled-data analogue microprocessor

  • P. DudekP. Hicks
  • Computer Science, Engineering
    2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)
  • 2000
The A/spl mu/P executes software programs, in a way akin to a digital microprocessor, while nevertheless operating on analogue sampled data values, which enables the design of mixed-mode systems which retain the speed/area/power advantages of the analogue signal processing paradigm while being fully programmable, general-purpose systems.

A new look at analogue computing using switched capacitor circuits

  • M. SobhyMostafa Y. Makkey
  • Computer Science, Physics
    ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)
  • 1998
An analogue computer base on switched capacitor circuits suitable for solving nonlinear differential equations in real time has been developed and the method has been used to solve nonlinear systems for the generation of Solitons.

Electronic analog and hybrid computers

Electronic analog and hybrid computers , Electronic analog and hybrid computers , مرکز فناوری اطلاعات و اطلاع رسانی کشاورزی

A new wide-band amplifier technique

Precision dc-coupled amplifiers having risetimes of less than a nanosecond have recently been fabricated using the monolithic planar process, characterized by a stage-gain- bandwidth product essentially equal to that of the transistors, and a very linear transfer characteristic, free from temperature dependence.

A precise four-quadrant multiplier with subnanosecond response

  • B. Gilbert
  • Engineering
    IEEE Solid-State Circuits Newsletter
  • 2007
Among the most signficant presentations in the 50-year history of the ISSCC, Barrie Gilbert's classic paper has become the fifth most frequently cited JSSC article and the first to be cited over 100 times.

A new 1.2 V BiCMOS log-domain integrator for companding current-mode filters

  • M. PunzenbergerC. Enz
  • Engineering
    1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96
  • 1996
New structures of differential and single-ended log-domain integrators are proposed, which can be used for very low supply voltage continuous-time filters. They offer a tuning range of several

Tunable BiCMOS continuous-time filter for high-frequency applications

A BiCMOS fully differential transconductor based on MOS transistors operating in the linear region is presented. The circuit has an equivalent nondominant pole located above 1.5 GHz. This makes it

The designer's guide to SPICE and Spectre

From the Publisher: The Designer's Guide to SPICE and Spectrer is an in-depth guide to circuit simulators from a designer's perspective: the pitfalls of circuit simulation, such as convergence and