A Unified Approach for IP Protection across Design Phases in a Packaged Chip

@article{Saha2010AUA,
  title={A Unified Approach for IP Protection across Design Phases in a Packaged Chip},
  author={Debasri Saha and Susmita Sur-Kolay},
  journal={2010 23rd International Conference on VLSI Design},
  year={2010},
  pages={105-110}
}
IP values contributed by the distinct design tools in specific design phases, are recognized by observing the signature of the owner of each tool as functional or scan mode output of the fabricated chip, for certain input vector secret to the owner. An existing approach inserts watermark through reordering of single scan chain, and solely identifies the owner of the logic design tool. Here we propose a novel scheme to watermark the recent reconfigurable scan architectures, operating in both… CONTINUE READING

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