# A Two's Complement Parallel Array Multiplication Algorithm

@article{Baugh1973ATC, title={A Two's Complement Parallel Array Multiplication Algorithm}, author={Charles R. Baugh and Bruce A. Wooley}, journal={IEEE Transactions on Computers}, year={1973}, volume={C-22}, pages={1045-1047} }

An algorithm for high-speed, two's complement, m-bit by n-bit parallel array multiplication is described. The two's complement multiplication is converted to an equivalent parallel array addition problem in which each partial product bit is the AND of a multiplier bit and a multiplicand bit, and the signs of all the partial product bits are positive.

## 687 Citations

### A high-speed two's complement bit-sequential multiplier

- Computer ScienceProceedings of TENCON'94 - 1994 IEEE Region 10's 9th Annual International Conference on: 'Frontiers of Computer Technology'
- 1994

A new algorithm for direct two's complement binary multiplication is presented that is fast and can easily be fabricated with VLSI technology.

### Two's complement parallel multiplier

- Mathematics
- 1998

A new two's complement parallel multiplier architecture is proposed. It is based on the partitioning of one of the operands into four groups. Array multipliers without the final adder are used to…

### A Two's Complement Array Multiplier Using True Values of the Operands

- Computer ScienceIEEE Transactions on Computers
- 1983

A new algorithm for implementing the two's complement multiplication of an m × n bit number is described, and a comparison with the Pezaris and Baugh-Wooley arrays is presented, showing that the new array is as fast as the PeZaris array and uses less hardware than the Baugh theooley implementation.

### A multioperand two's complement addition algorithm

- Computer Science1985 IEEE 7th Symposium on Computer Arithmetic (ARITH)
- 1985

A novel algorithm for summing a set of 2's complement numbers in parallel by simply complementing all the sign bits, suitable for computer-aided design of custom VLSI.

### Two's-complement fast serial-parallel multiplier

- Computer Science
- 1995

It is shown that sign extension of the sum or carry bit, produced during the addition of the bit product rows, can be avoided, and a more efficient multi- plier can be obtained.

### Parallel Encryted Array Multipliers

- Computer ScienceIBM J. Res. Dev.
- 1988

An algorithm for direct two's-complement and sign-magnitude parallel multiplication is described, which produces the multiplication with fewer than the minimal number of rows required for a direct multiplication process.

### Fast Parallel Algorithms for Binary Multiplication and Their Implementation on Systolic Architectures

- Computer ScienceIEEE Trans. Computers
- 1989

Two algorithms for parallel multiplication of two n-bit binary numbers using column compression to increase the speed of execution and can be easily modified to handle two's complement numbers with constant differences in time are presented.

### A new parallel multiplication algorithm and its VLSI implementation

- Computer ScienceCSC '88
- 1988

The proposed algorithm computes the product in 31og2n units of time of a single bit full-adder and is easily implemented on a suitable VLSI architecture using less than n(n + (1/2) log2n)/2 processing elements.

### Algorithms for Iterative Array Multiplication

- Computer ScienceIEEE Transactions on Computers
- 1986

The regular interconnection structures of the multiplier array cell elements, which are ideal for VLSI implementation, are described and the speed and hardware complexity of two new iterative array algorithms, both of which require n-cell delays, are compared.

### Multiplexer-based array multipliers

- Mathematics
- 1999

A new algorithm for the multiplication of two n-bit numbers based on the synchronous computation of the partial sums of the two operands is presented. The proposed algorithm permits an efficient…

## References

### A 40-ns 17-Bit by 17-Bit Array Multiplier

- Computer ScienceIEEE Transactions on Computers
- 1971

A high-speed array multiplier generating the full 34-bit product of two 17-bit signed (2's complement) numbers in 40 ns is described. The multiplier uses a special 2-bit gated adder circuit with…