A Two's Complement Parallel Array Multiplication Algorithm

@article{Baugh1973ATC,
  title={A Two's Complement Parallel Array Multiplication Algorithm},
  author={Charles R. Baugh and Bruce A. Wooley},
  journal={IEEE Transactions on Computers},
  year={1973},
  volume={C-22},
  pages={1045-1047}
}
  • C. Baugh, B. Wooley
  • Published 1 December 1973
  • Computer Science, Mathematics, Physics
  • IEEE Transactions on Computers
An algorithm for high-speed, two's complement, m-bit by n-bit parallel array multiplication is described. The two's complement multiplication is converted to an equivalent parallel array addition problem in which each partial product bit is the AND of a multiplier bit and a multiplicand bit, and the signs of all the partial product bits are positive. 

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References

A 40-ns 17-Bit by 17-Bit Array Multiplier

  • S. Pezaris
  • Computer Science
    IEEE Transactions on Computers
  • 1971
A high-speed array multiplier generating the full 34-bit product of two 17-bit signed (2's complement) numbers in 40 ns is described. The multiplier uses a special 2-bit gated adder circuit with