A Traffic Model for Routing Logic in Network On Chip

@inproceedings{Merline2015ATM,
  title={A Traffic Model for Routing Logic in Network On Chip},
  author={C. G. Joy Merline and R. S. Niveditha},
  year={2015}
}
The increased demand for on-chip communication bandwidth as a result of the multi-core trend has made packet-switched networks-on-chip (NoCs) a more compelling choice for the communication backbone in next-generation systems. However, NoC designs have many issues like power, area, and performance trade-offs in topology, buffer sizes, routing algorithms and flow control mechanisms— hence the study of new NoC designs can be very time intensive. The effectiveness of the NoC system can be found by… CONTINUE READING

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