A Trace Cache Microarchitecture and Evaluation

  title={A Trace Cache Microarchitecture and Evaluation},
  author={Eric Rotenberg and Steve Bennett and James E. Smith},
  journal={IEEE Trans. Computers},
As the instruction issue width of superscalar processors increases, instruction fetch bandwidth requirements will also increase. It will eventually become necessary to fetch multiple basic blocks per clock cycle. Conventional instruction caches hinder this effort because long instruction sequences are not always in contiguous cache locations. Trace caches overcome this limitation by caching traces of the dynamic instruction stream, so instructions that are otherwise noncontiguous appear… CONTINUE READING
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