A Test Circuit for Measurement of Clocked Storage Element Characteristics


We present a method, on-chip test circuitry, and an error analysis, for accurate measurement of timing characteristics and power consumption of clocked storage elements. The test circuit was fabricated in 0.11 m CMOS technology and the measurements performed automatically using a serial scan interface. The precision and accuracy of the presented method are demonstrated by the ability to measure entire clock-to-output characteristics of flip-flops. Estimated data-to-output delay systematic measurement error is 6 ps (7%), and random error is 10 ps (11%). The method and the test circuit are applicable for delay measurements of other circuit blocks as well.

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@inproceedings{Nedovic2004ATC, title={A Test Circuit for Measurement of Clocked Storage Element Characteristics}, author={Nikola Nedovic and William W. Walker and Vojin G. Oklobdzija}, year={2004} }