A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms

Abstract

A very simple multiplier cell is developed for use in a linear, purely systolic array forming a digit-serial multiplier for unsigned or 2'complement operands. Each cell produces two digit-product terms and accumulates these into a previous sum of the same weight, developing the product least signiicant digit rst. Grouping two terms per cell, the ratio of active elements to latches is low, and only n 2 cells are needed for a full n by n multiply. A modulo-multiplier is then developed by incorporating a Montgomery type of modulo-reduction. Two such multipliers interconnect to form a purely systolic modulo exponentiator, capable of performing RSA encryption at very high clock frequencies, but with a low gate count and small area. It is also shown how the multiplier, with some simple back-end connections, can compute modular inverses and perform modular division for a power of two as modulus.

DOI: 10.1109/12.295851

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@article{Kornerup1994ASL, title={A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms}, author={Peter Kornerup}, journal={IEEE Trans. Computers}, year={1994}, volume={43}, pages={892-898} }