A Systolic-Array Architecture for First-Order 3-D IIR Frequency-Planar Filters

@article{Madanayake2008ASA,
  title={A Systolic-Array Architecture for First-Order 3-D IIR Frequency-Planar Filters},
  author={Arjuna Madanayake and Leonard T. Bruton},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
  year={2008},
  volume={55},
  pages={1546-1559}
}
A massively parallel systolic-array architecture is proposed for the implementation of real-time VLSI spatio-temporal 3-D IIR frequency-planar filters at a throughput of one-frame-per-clock-cycle (OFPCC). The architecture is based on a differential-form transfer function and is of low circuit complexity compared with the direct-form architecture. A 3-D look-ahead (LA) form of the transfer function is proposed for maximizing the speed of the implementation, which has a nonseparable 3-D transfer… CONTINUE READING
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