A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms

@article{Kornerup1994ASL,
  title={A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms},
  author={Peter Kornerup},
  journal={IEEE Trans. Computers},
  year={1994},
  volume={43},
  pages={892-898}
}
A very simple multiplier cell is developed for use in a linear, purely systolic array forming a digit-serial multiplier for unsigned or 2'complement operands. Each cell produces two digit-product terms and accumulates these into a previous sum of the same weight, developing the product least significant digit first. Grouping two terms per cell, the ratio of active elements to latches is low, and only upper bound [n]/2 cells are needed for a full n by n multiply. A module-multiplier is then… 
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