A Systematic Design Methodology for Low-Power NoCs


Network-on-chip (NoC) communication architectures are emerging as the most scalable and efficient solution to handle on-chip communication challenges in the multicore era. In NoCs, power estimations in the early stages of the design help the designers to optimize the design for energy consumption and efficiently map applications to achieve low-power… (More)
DOI: 10.1109/TVLSI.2013.2296742

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