Corpus ID: 18795884

A Survey of VLSI Techniques for Power Optimization and Estimation of Optimization

  title={A Survey of VLSI Techniques for Power Optimization and Estimation of Optimization},
  author={N. Sharma and M. Kaur},
  • N. Sharma, M. Kaur
  • Published 2014
  • With the advancement in compact, portable and high-density micro-electronic devices and systems, the power dissipated in very large scale integrated (VLSI) design circuits has become a critical concern. Accuracy and efficiency in power estimation involvedin the design phase is important in order to meet power specifications without high cost redesign process. This paper, presents a review of the power optimization theory approach and the estimation techniques of recent proposition. VLSI design… CONTINUE READING
    4 Citations


    On the Optimal Drivers for High-Speed Low Power ICs
    • 17
    Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution
    • 164
    • PDF
    Short-circuit energy dissipation modeling for submicrometer CMOS gates
    • 29
    A New Area and Shape Function Estimation Technique for VLSI Layouts
    • 29
    • PDF
    Sensor Networks With Random Links: Topology Design for Distributed Consensus
    • 240
    • PDF
    • Nikolic, "Power-performance optimization for custom digital circuits," Proc. PATMOS’05, LNCS 3728, Leuven, Belgium, September 20-23
    • 2005
    Optimal redistribution of white space for wire length minimization
    • 22
    • Ruiz de Clavijo, C. J. Jiménez, M. Valencia, "Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level", Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation Lecture Notes in Computer Science Volume 2451
    • 2002